• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Device (WD +) for monitoring a clock generator (μC Clock), generating a periodic rate signal (ECLK). The device comprises means for monitoring the duration of the pulse (Tpeclkd) of the clock signal (ECLK).
    公开号:FR3015151A1
    申请号:FR1462650
    申请日:2014-12-17
    公开日:2015-06-19
    发明作者:Hartmut Schumacher；Ruediger Karner
    申请人:Robert Bosch GmbH；
    IPC主号:
    专利说明:

    [0001] Field of the Invention The present invention relates to a device and method for monitoring a clock generator, and a device for monitoring a clock generator, the clock generator generating a periodic rate signal. State of the art Current vehicle safety systems have multi-level monitoring components called watchdogs. There is a distinction between "watchdogs" of circuits and "watchdogs" of programs. In the first level, a "watchdog" monitors the frequency of a system clock generator that provides from a microprocessor (pC), for example by dividing the frequency of its own clock generator. interface, synchronously, other internal or external components, electrical or electronic or digital. In other floors, you have to answer the "watchdog" questions correctly to the microprocessor. The questions can be, for example queries such as calculated calculation missions. The microprocessor resources required to respond to queries or queries can be composed individually, in particular from the microprocessor functions used in the applications in corresponding program plans. The programming of the "watchdog" requirement ensures that the correct answer to questions can only be done by a correct sequence of application programs. There are thus levels of "watchdogs" for each program plan (real-time program, background program, etc.). According to a more specific variant, the correct responses of the microprocessor are provided to the different stages of "watchdogs" (real-time program, background program, etc.) in a certain predefined time window. Systems that make decisions in the shortest time, that is to say in less than two milliseconds, such as, for example, personal protection means control systems equipping a vehicle must detect in time the defects which could lead to erroneous behavior, for example the unwanted activation of the means of protection of persons. This is currently done by monitoring the frequency of the clock generator of the microprocessor system by a watchdog. Any defect of the oscillator in the microprocessor is thus detected. The oscillator may be in the form of a quartz or a resonator. OBJECT OF THE INVENTION The present invention aims to overcome the drawbacks of the known systems and their complexity and proposes to develop additional monitoring of the working ratio of the clock generator of the system with the aid of FIG. 'a watchdog' circuit. DESCRIPTION AND ADVANTAGES OF THE INVENTION The solution of the invention has the advantage that the defects which can cause a modification of the pulse duration, the working ratio / duty ratio such as the damping of the signal supplied by the generator system clock is detected on the transmission path of the signal generator which is typically the microprocessor to the associated circuit components (eg ASIC), interface components or the like, with Redundant functions (eg a multi-channel interface to external sensors) can lead to a malfunction of separate components or several connected components and thus the possible failure of the entire system. This is particularly important if the linked circuit components use both the rising edge and the falling edge of the external system clock generator signal in the digital state machines, data transfer functions, units detection or similar means. The device according to the invention comprises means for monitoring the pulse duration of a clock signal or clock signal. The monitored clock signal is provided by a clock generator, in particular for a device for managing the person protection means in a vehicle which generates a periodic clock signal. The additional monitoring of the pulse duration of the clock signal (clock signal) is, among other things, important if digital components use to operate both the rising edge and the falling edge of the clock signal or signal of the clock. - s dence. The pulse duration is the time between the rising edge and the falling edge of the rate signal. According to an advantageous development of the invention, the device generates a blocking signal, in particular for blocking the personal protection means as a function of the surveillance signal. The advantageous embodiment of the invention makes it possible effectively to avoid that a defect generates a defective operation such as the activation of personal protection means or the endangerment of persons or property. Advantageously, the device comprises means for capturing the pulse duration. These means for entering the pulse duration comprise a counter. The counter is clocked by a separate clock generator and it captures the time between the rising edge and the falling edge of the clock signal or monitored clock signal, for example by starting a counter (for example). example by the rising edge) and stopping the counter (for example by the falling edge) of the clock signal or clock signal monitored. At the end of a pulse length, the count state is compared to a threshold. According to an advantageous development, the counting state is compared with a predefined upper threshold and a predefined lower threshold. The threshold or thresholds depend on the normalized, predictable pulse duration of the clock generator. This makes it possible to monitor the clock generator simply and economically. According to one variant, the device comprises a capacitor and a comparator, in particular a comparator with a window for entering the pulse duration. This advantageous development constitutes a simple and economical embodiment of the invention. The use of simple electronic components (capacitor and comparator or window comparators) results in a robust device. This embodiment is based on the fact that the charge level of the capacitor is compared by a comparator to a reference voltage. According to an advantageous development of this embodiment, the comparator is a window comparator comparing the charge or charge level of the capacitor to at least two reference voltages. The two reference voltages correspond, for example, to a lower predictable charge level and a higher predictable charge level. Starting, for example, with the rising edge of the monitored clock signal provided by the clock generator, the capacitor is charged which discharges immediately at the beginning of the pulse pause. The position of the comparator or window comparator which indicates whether the charge state of the reference capacitor (equivalent to the pulse duration) is below or above a predictable level (reference voltage) or is inside or outside the monitoring window constituted by the two reference voltages, is stored in the memory by the falling edge of the clock signal supplied by the clock generator. If the reference capacitor charge level is at least one threshold (reference voltage) then the pulse duration corresponds to the minimum expected duration and the clock generator monitoring corresponds to a positive result. vis-à-vis the minimum length of the pulse duration.
    [0002] If the charge level of the reference capacitor is, in the monitoring band, defined by a reference voltage higher than a lower reference voltage, then the duration of the pulse is between the upper monitoring limit and the lower limit. lower monitoring so that the monitoring of the clock generator gives a positive result for the pulse duration. The realization of the invention by the process is important. The method according to the invention can be applied by a control element and in particular the control device of the vehicle's personal protection means. A program is recorded in the control element which is applied by a computer including a microprocessor or a signal processor and applies the method of the invention. The invention is thus realized by the program recorded in the control element so that this control element operating with this program applies the invention in the same way as the process itself for the implementation of the program. gram. The control element can in particular apply an electrical memory medium, for example a read-only memory. Drawings The present invention will be described hereinafter in more detail with the aid of examples of monitoring devices according to the invention shown in the accompanying drawings in which: - Figure 1 is a block diagram of a device with a clock generator; - FIG. 2 is a block diagram of a verification device 15 of a clock generator according to the state of the art, - FIG. 3 is a block diagram of FIG. A first embodiment of the device for checking or checking a clock generator according to the invention; FIG. 4 is a block diagram of an alternative embodiment of the device for verifying a generator of a generator; According to the invention, FIG. 5 very schematically shows a flow chart of the method of the invention. DESCRIPTION OF EMBODIMENTS OF THE INVENTION FIG. 1 shows a block diagram of a device including a clock generator. The oscillator-shaped clock generator of the illustrated embodiment is associated with a microcontroller pC. The oscillator-shaped clock generator transforms the mechanical oscillations of the crystal (for example a quartz or alternatively a resonator) into an electrical oscillation and thus generates the base frequency called the base clock. From this basic clock, a rate signal ECLK is formed for example by frequency division. This clock signal is often called "external clock". The microcontroller pC supplies the ECLK clock signal thus formed to digital components, for example to a SCON security component for synchronous digital control. In the embodiment shown, the SCON security component includes interfaces, for example SPI, PSI, and a WD circuit watchdog. The "watchdog" circuit also includes an oscillator-shaped clock generator WD, for example an RC oscillator whose frequency is defined by an external resistance connected to ground. The "watchdog" circuit WD includes functions to block the triggering of the person protection means (power blocking stage). External xIS sensors are connected to the PSI interfaces. In, this presentation x can be replaced for example by S or F which gives SIS = lateral impact sensor, that is to say a sensor which detects lateral shocks and FIS, that is to say a frontal impact sensor, that is to say a sensor that detects frontal collisions. FIG. 2 shows a block diagram of a device for checking (or checking) a clock generator according to the state of the art. The clock generator to check and the pC Clock internal generator of the microcontroller pC. The internal clock generator pC Clock gives a periodic clock signal ECLK from which the clock generator (for example a quartz, a resonator or similar means) with a frequency for example of n MHz. The ECLK timing signal to be checked having a certain period duration (or more simply "period") Teclk is applied to a WD monitoring device. This usually includes an upstream divider for dividing the timing signal ECLK appropriately to suit the boundary conditions of the device to be monitored WD (eg for the maximum processing speed etc.). The upstream divider can usually receive values between 1 and 1024. The monitoring device WD is the most sensitive for the value 1. The duration of the period Teclkd of the rate signal ECLK divided by the upstream divider is called "ECLKd" ; this signal is then measured by a WD counter which is clocked by a reference oscillator WD CLOCK. The duration of the period Twd of the counter WD Counter is dependent in the present embodiment of the expected duration of the period of the clock generator. The WD counter has processing logic with the START function to start the WD Counter, the STOP function to stop the WD counter, the RESET function to reset the WD counter. Counter and the "READ" function to read the count status of the WD counter. After each ECLKd period, compare (compare) the count state to an upper limit value (WD smax) or a lower limit value (WD smin). These limit values are in a suitable memory or in a wired device. The counter is then reset (RESET) to start "START" again. If the count state is outside the monitoring terminal for the split rate signal ECLKd, the safety functions can be blocked. FIG. 3 is a block diagram of an embodiment according to the invention of the monitoring device of a clock generator WD + (= watch dog period duration + watch dog pulse duration). In addition to the state of the art (period duration), the duration of the pulse of the clock signal or ECLK clock signal is measured. The duration of the pulse is the time between a rising edge and a falling edge of the clock signal. For this, the pulse duration of Tpelckd of the divided rate signal ECLKd is measured with a frequency controlled counter by a reference oscillator at the frequency WD +. After each pulse duration ECLKd, the comparison (COMPARE) of the counting state is carried out with an upper limit value or a lower limit value which defines a tolerance band (WD + smin, WD + smax) around the duration of Predictable impulse Tpeclkd. Then the WD counter (RESET) is reset or reset and the next positive edge is restarted according to the embodiment shown. If the count state of the counter WD + is in the monitoring band for the pulse duration Teclkd and the count state of the counter WD is in the monitoring band of the period duration Teclkd, and it There is no blocking of the safety functions because the frequency and pulse duration and thus the duty cycle (working ratio = pulse duration / period duration) of the clock generator are correct.
    [0003] Figure 4 is a block diagram of an alternative embodiment of the device according to the invention for checking a clock generator. In this case, a capacitor Cref is charged with a constant current I during the high linear phase ECLKd and is discharged with the start of the pulse pause ECLKd by a sudden discharge (fast discharge). With a window comparator, one verifies the voltage uc across the capacitor Cref to determine if the load is in the band defined by Vref u and Vref o. The reference Vref u represents the minimum load and Vref o represents the maximum upper load of the capacitor. The state at the instant of the falling edge of the signal ECLKd pulse is stored in a memory FlipFlop FF (if in the band we have: Q = 1, if outside the band we have: Q = 0). If the voltage uc of the capacitor Cref at the moment of the falling edge of the pulse is outside the band, this means that the pulse duration of the clock generator ECLK clock signal is not correct and so, even if the ECLK clock signal frequency is adequate, the duty ratio (pulse duration / period duration) is not good. The frequency of the clock signal is thus monitored, for example with the monitoring device of a known clock generator according to the state of the art (see Fig. 1) so that this means is not FIG. 5 is a very schematic flow diagram of the application of the method. In step 501, the clock generator pC Clock generates a clock signal (or clock signal). In step 502, the duration of the pulse of the cadence signal is monitored. 30 NOMENCLATURE OF MAIN ELEMENTS pC pC Clock microcontroller Internal clock generator COMPAR Cref comparison FF capacitor FlipFlop ECLK Cadence signal / ECLKd signal clock split rate FIS Impact or frontal impact sensor RESET Resetting the SCON counter Security component SPI, PSI Interface (s) SIS Lateral impact sensor START Starting the counter STOP Teclk counter stop Duration of period Twd Duration of period uc Voltage across the capacitor Vref_U Lower limit of the voltage band Vref_O Upper limit of the WD band Circuit guard dog WD smax Upper limit value of the count state WD smin Lower limit value of the count state25
    权利要求:
    Claims (14)
    [0001]
    CLAIMS 1 °) Device (WD +) for monitoring a clock generator (pC Clock), which generates a periodic rate signal (ECLK), characterized in that it comprises means for monitoring the duration of the pulse (Tpeclkd ) of the clock signal (ECLK).
    [0002]
    2 °) Device (WD +) according to claim 1, characterized in that the clock generator (pC Clock) is a clock generator (pC Clock) for a control device of a means for protecting people in a vehicle and the device (WD +) generates a blocking signal to block the control of the person protection means according to the monitoring.
    [0003]
    3) Device according to claim 1, characterized in that it comprises means including a counter (WD + Counter) for entering the pulse duration (Tpeclkd).
    [0004]
    4) Device according to claim 3, characterized in that it comprises a second clock generator (WD + Clock) and in particular the device (WD +) controls the counter (WD + Counter) using the second clock generator (WD + Clock).
    [0005]
    5 °) Device according to claim 3, characterized in that it comprises means for capturing the pulse duration (Tpeclkd) of at least one capacitor (Cref) and at least one comparator, including a window comparator.
    [0006]
    6 °) Device according to claim 1, characterized in that it comprises comparison means (Compare) of the pulse duration (Tpeclkd) to at least one threshold (WD + smin, WD + smax, Vref u, Vref o) .
    [0007]
    7 °) Device according to claim 6, characterized in that it generates a blocking signal if the pulse duration (Tpeclkd) is lower than a lower threshold (WD + smin, Vref u) or is greater than a higher threshold ( WD + -smax, Vref o).
    [0008]
    8 °) Method (500) for monitoring a clock generator which generates (501) a periodic clock signal (ECLK), characterized by monitoring (502) the pulse duration (Tpeclkd) of clock signal.
    [0009]
    Method (500) according to claim 8, characterized in that the clock generator (pC Clock) is a clock generator for a control device of a means for protecting persons of a vehicle and depending on the monitoring, it generates a blocking signal to block the control of the personal protection means.
    [0010]
    Method (500) according to claim 8, characterized in that the pulse duration (Tpeclkd) is entered by means of a counter (WD + Counter).
    [0011]
    11 °) Method (500) according to claim 8, characterized in that the pulse duration (Tpeckld) is entered as a function of the state of at least one capacitor (Cref).
    [0012]
    12 °) Method (500) according to claim 8, characterized in that the pulse duration is compared with at least one threshold (WD + smin, WD + smax, Vref u, Vref o).
    [0013]
    13 °) Method (500) according to claim 9, characterized in that a blocking signal is generated if the pulse duration (Tpeckld) is lower than a lower threshold (WD + smin, Vref u) or greater than a threshold higher (WD + -smax, Vref o).
    [0014]
    14 °) control device comprising a device (WD +) according to any one of claims 1 to 7 and / or configured to perform a method (500) according to one of claims 8 to 13.15
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    法律状态:
    2015-12-18| PLFP| Fee payment|Year of fee payment: 2 |
    2016-12-21| PLFP| Fee payment|Year of fee payment: 3 |
    2017-12-19| PLFP| Fee payment|Year of fee payment: 4 |
    2018-08-10| PLSC| Search report ready|Effective date: 20180810 |
    2018-12-18| PLFP| Fee payment|Year of fee payment: 5 |
    2019-12-19| PLFP| Fee payment|Year of fee payment: 6 |
    2021-09-10| ST| Notification of lapse|Effective date: 20210806 |
    优先权:
    申请号 | 申请日 | 专利标题
    DE102013226429.1A|DE102013226429A1|2013-12-18|2013-12-18|Apparatus and method for monitoring a timer|
    DE102013226429.1|2013-12-18|
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